P1 - Phunsy bus:

A 1	+5 Volt		div		C 1	+5 Volt		div
A 2	x				C 2	D7		P4-04
A 3	x				C 3	D6		P4-05
A 4	x				C 4	D5		P4-11
A 5	x				C 5	D4		P4-10
A 6	x				C 6	D3		P4-09
A 7	x				C 7	D2		P4-08
A 8	DispmemReq	P3-15		C 8	D1		P4-07
A 9	PromReq		P3-16		C 9	DO		P4-06
A1O	OpAck•		P13-14		C1O	WRP		P5-10
A11	x				C11	R/W•		P5-13
A12	WritExtReq	P3-5		C12	OPREQ		P5-15
A13	ReadExtReq	P5-14		C13	M/IO•		P5-01
A14	x				C14	A14-D/C•	P5-02
A15	x				C15	A13-E/NE•	P5-11
A16	x				C16	A12		P5-06
A17	x				C17	A11		P2-01
A18	unused (IRQ in)			C18	A1O		P2-04
A19	unused (IRQ out)		C19	A 9		P2-15
A20	x				C20	A 8		P2-09
A21	x				C21	A 7		P2-08
A22	x				C22	A 6		P2-06
A23	x				C23	A 5		P2-07
A24	x				C24	A 4		P2-13
A25	x				C25	A 3		P2-16
A26	x				C26	A 2		P2-11
A27	x				C27	A 1		P2-10
A28	x				C28	A 0		P2-05
A29	RESET•		P3-7		C29	x
A30	x				C30	Clock• 14 MHz	P5-3
A31	GND		div		C31	GND		div
A32 @	+12 Volt			C32 @	-5 Volt	

@ = not from main CPU board
• = inverted

DispmemReq = A14• A13• A12 A11• OpReq  (0x1000 to 0x17ff and OpReq, combine with M/IO•)
PromReq    = A14• A13• A12 • OpReq  (0x000 to 0xfff and OpReq, combine with M/IO• and R/W•)

WritExtReq = (R/W•)• (M/IO•)• A13-E/NE• OpReq
ReadExtReq =  R/W•   (M/IO•)• A13-E/NE• OpReq